NVIDIA announced that Denver would have a L1 instruction cache and 128 KB of L1 cache 64 KB of data. It quite unusual for unbalanced L1 I / D caches in a client machine, I can only assume has something to do with Denver more unique architecture. Curiously, the Efficeon processor (second generation of code morphing CPU) had exactly the same size of L1 cache (he also worked on eight large VLIW instructions for what it's worth).
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